This invention relates generally to processing within a computing environment, and more particularly to enhancing modularity in heterogeneous 3D stacks.
In computer chip manufacturing, three-dimensional (3D) stacks use layers of components, such as processing chips and memory that are combined in a way that decreases the distance that data must travel between the components. The decreased distance between components results in faster data rates and lower heat as a result of less electrical resistance.
Modularity and heterogeneous integration are important advantages of 3D technology, yet they are limited to same size chips. In the case of heterogeneous chip sizes, efficient use of silicon in chip layers containing accelerator chips or redundancy layers is challenging since these layers tend to be smaller than the main processor chip itself. Integrating chips which are smaller than the main processor chip results in either the use of silicon as a filler to extend the chips to the same dimensions as the main processor, or results in air gaps in the layers which contain the smaller chips. Using extra silicon is inefficient, and leaving air space creates uneven heat dissipation resulting in hot spots on the chips. However, integrating smaller and less complicated layers, such as accelerators/redundancies, has clear yield and cost advantages, because chip size and complexity are major determinants of yield. The thermal interface material between the silicon layers and the lid, or heat sync, may not have full coverage if the smaller chips are placed between the heat sync and main processor. In addition, aligning these smaller chips can present issues, as the underlying main processor, which is typically much larger than these smaller chips, does not easily lend itself to layer alignment procedures with chips of varying sizes.